A 6.2mW 7b 3.5GS/s time interleaved 2-stage pipelined ADC in 40nm CMOS

A 6.2mW 7b 3.5GS/s time interleaved 2-stage pipelined ADC in 40nm CMOS ■

Annachiara Spagnolo, Bob Verbruggen, Stefano D'Amico, Piet Wambacq

Abstract ■

A 7b time interleaved hybrid ADC in 40nm CMOS is presented. The ADC consists of two pipelined stages and combines an intrinsically linear SAR with a fully calibrated binary search architecture to achieve energy efficiency. The first stage of each channel consists of a 3b SAR followed by a dynamic amplifier merged with a comparator. The second stage is a 3b comparator-based asynchronous binary search with threshold calibration to compensate amplifier nonlinearity. The calibration references are generated on chip by using the DAC embedded in the first stage. The prototype achieves a peak SNDR of 38dB at 3.5GS/s while consuming approximately 6.2mW.