With the increasing cost of scaled CMOS, effort is spent in maximizing performance attainable in already available technologies. Above-IC technology (A-IC), consisting of a 5 ? m thick electroplated Cu layer on an 18 micron low-K BCB dielectric, post-processed on top of the CMOS, provides a low-cost solution to achieve high-Q passive devices, with relaxed mask requirements. A technique is presented to fully layout a VCO under its A-IC inductor, by using a two-layer shield in the top layers of the CMOS back-end, enabling 3D integration of active circuitry and high-Q passives. The technique is demonstrated on an LC-VCO in 45nm bulk CMOS, that consumes only 400 ? W, and occupies a low area of 0.12mm2.