A 57-to-66GHz Quadrature PLL in 45nm Digital CMOS

A 57-to-66GHz Quadrature PLL in 45nm Digital CMOS ■

Karen Scheir, Gerd Vandersteen, Yves Rolain, Piet Wambacq

Abstract ■

A 57-to-66GHz quadrature PLL in low-power 45nm digital CMOS achieves a large tuning range with 2 QVCOs and a tunable injection-locked prescaler. The circuit has quadrature outputs, consumes 78mW from a 1.1V supply, achieves a phase noise of -82dBc/Hz at 3MHz offset around 61.6GHz, and has a reference spur level of -42dBc.