Advanced planar bulk and multigate CMOS technology: analog-circuit benchmarking up to mm-wave frequencies

Advanced planar bulk and multigate CMOS technology: analog-circuit benchmarking up to mm-wave frequencies ■

Piet Wambacq, Abdelkarim Mercha, Karen Scheir, Bob Verbruggen, Jonathan Borremans, Vincent De Heyn, Steven Thijs, Dimitri Linten, Geert Van Der Plas, Bertrand Parvais, Morin Dehan, S. Decoutere, Charlotte Soens, Nadine Collaert, M. Jurczak

Abstract ■

CMOS scaling beyond 45nm requires devices that deviate from the planar bulk transistor with a polysilicon gate and nitrided silicon dioxide (SiON) as gate dielectric. To downscale planar bulk devices, strain is used to boost mobility and new materials are introduced in the gate stack. Multigate devices such as fully-depleted SOI FinFETs (Fig. 29.4.1) are also candidates for downscaling beyond 45nm.