Advanced planar bulk and multigate CMOS technology: analog-circuit benchmarking up to mm-wave frequencies

Advanced planar bulk and multigate CMOS technology: analog-circuit benchmarking up to mm-wave frequencies ■

Piet Wambacq, Piet Wambacq, Piet Wambacq, Abdelkarim Mercha, Abdelkarim Mercha, Abdelkarim Mercha, Karen Scheir, Karen Scheir, Karen Scheir, Bob Verbruggen, Bob Verbruggen, Bob Verbruggen, Jonathan Borremans, Jonathan Borremans, Jonathan Borremans, Vincent De Heyn, Vincent De Heyn, Vincent De Heyn, Steven Thijs, Steven Thijs, Steven Thijs, Dimitri Linten, Dimitri Linten, Dimitri Linten, Geert Van Der Plas, Geert Van Der Plas, Geert Van Der Plas, Bertrand Parvais, Bertrand Parvais, Bertrand Parvais, Morin Dehan, Morin Dehan, Morin Dehan, S. Decoutere, S. Decoutere, S. Decoutere, Charlotte Soens, Charlotte Soens, Charlotte Soens, Nadine Collaert, Nadine Collaert, Nadine Collaert, M. Jurczak, M. Jurczak, M. Jurczak

Abstract ■

CMOS scaling beyond 45nm requires devices that deviate from the planar bulk transistor with a polysilicon gate and nitrided silicon dioxide (SiON) as gate dielectric. To downscale planar bulk devices, strain is used to boost mobility and new materials are introduced in the gate stack. Multigate devices such as fully-depleted SOI FinFETs (Fig. 29.4.1) are also candidates for downscaling beyond 45nm.