ESD Protection for 5.5 GHz LNA in 90 nm RF CMOS - Implementation Concepts, Constraints and Solutions
 
ESD Protection for 5.5 GHz LNA in 90 nm RF CMOS - Implementation Concepts, Constraints and Solutions ■
 
S. Thijs, Mahadeva Iyer Natarajan, Dimitri Linten, V. Vassilev, T. Daenen, A.j. Scholten, R. Degraeve, Piet Wambacq, G. Groeseneken
 
Abstract ■

Design and implementation of ESD protection for a 5.5 GHz Low Noise Amplifier (LNA) fabricated in a 90 nm RF CMOS technology is presented. An on-chip inductor, added as 'plug-and-play',is used as ESD protection for the RF pins. The consequences of design and process, as well as the limited freedom on the ESD protection implementation for all pins to be protected are presented in detail and additional improvements are suggested.