VHDL Synthesis of a 0.7 µ CMOS ASIC for block segmentation of digital images
 
VHDL Synthesis of a 0.7 µ CMOS ASIC for block segmentation of digital images ■
 
J. Huylebroeck, J. Huylebroeck, J. Huylebroeck, D. Martiny, D. Martiny, D. Martiny, Piet Boekaerts, Piet Boekaerts, Piet Boekaerts, Jan Cornelis, Jan Cornelis, Jan Cornelis