Thermal challenges in 3D-IC arise from the high thermal resistance of the 3D interface layer and Back-End-Of-Line (BEOL), leading to poor heat dissipation \& increased peak junction temperature. In this study we analyze the impact of technology and material parameters of Embedded micro-Bumps (E-μ Bumps) and Wafer-to- Wafer (W2W)-Hybrid Bonding (HB) on thermal behaviour of the package stack. Thermal analysis is conducted on a 64-core SoC with power density of 140\textbackslash{} W/cm2 using advanced A14 nanosheet CMOS technology. Simulation outcomes demonstrate that as the amount of metal in the 3D interface increases (relative to dielectric) from 0\% to 20\%, the peak temperature Tmax of E-μ Bumps decreases by 20\%, beyond which Tmax is limited by the BEOL thermal resistance. The study demonstrates that at 20\% metal density, the thermal impact of stand-off height is negligible, regardless of 3D interface technology. Among 2-die stacks, Memory-on-Logic (MoL) configuration exhibits the highest Tmax, 5°C above the 2D baseline, while 3-tier stack increase Tmax by 12°C, necessitating an extra 33\% heat transfer efficiency to reduce Tmax. Additionally, for BEOL analysis, introducing backside PDN, results in 2°C increase for 2D and 2°C reduction for 3D (MoL) configurations.