Toward 0 V ESD Protection in 2.5D/3D Advanced Bonding Technology

Toward 0 V ESD Protection in 2.5D/3D Advanced Bonding Technology ■

Shih-Hsiang Lin, Marko Simicic, Nicolas Pantano, Shih-Hung Chen, Geert Van Der Plas, Eric Beyne, Piet Wambacq

Abstract ■

This paper presents a methodology to help prevent overdesign of Electrostatic Discharge (ESD) protection circuits for internal I/O in 2.5D/3D bonding technologies. We explore how the voltage suppression effect mitigates voltage-driven gate oxide breakdown during stacking and emphasize the role of series resistance in reducing peak discharge current. Our findings indicate that highly variable non-contact discharges are not a concern in advanced bonding technologies, shifting the focus to more predictable contact discharges. Also, we provide guidelines to design efficient ESD protection circuits for internal IO in 2.5D/3D stacked system.