ESD mitigation for 3D IC hybrid bonding

ESD mitigation for 3D IC hybrid bonding ■

, , , Marko Simicic, Marko Simicic, Marko Simicic, Nicolas Pantano, Nicolas Pantano, Nicolas Pantano, Shih-Hung Chen, Shih-Hung Chen, Shih-Hung Chen, Philippe Roussel, Philippe Roussel, Philippe Roussel, Geert Van Der Plas, Geert Van Der Plas, Geert Van Der Plas, Eric Beyne, Eric Beyne, Eric Beyne, Piet Wambacq, Piet Wambacq, Piet Wambacq

Abstract ■

Three-dimensional (3D) die-stacking has become a promising way to continue improving the integrated circuits performance. However, the risk of electrostatic discharge (ESD) during the stacking process is not yet fully understood. In this paper, we focus on understanding the electrostatics before the contact moment for the 3D stacking process. Our findings indicate that the stacking process presents a relatively low risk of ESD.