Cryogenic temperature DC-IV measurements and compact modeling of n-channel bulk FinFETs with 3–4 nm wide fins and 20 nm gate length for quantum computing applications

Cryogenic temperature DC-IV measurements and compact modeling of n-channel bulk FinFETs with 3–4 nm wide fins and 20 nm gate length for quantum computing applications ■

Sumreti Gupta, Aarti Rathi, Bertrand Parvais, Abhisek Dixit

Abstract ■

CMOS circuits for Quantum Computing applications require FETs operating at cryogenic temperatures. In this work, we aim to present one of the first insights on the ability of the industry standard compact model BSIMCMG in capturing low temperature device physics. We have performed wafer-level DC-IV measurements on multi-fin n- channel bulk FinFETs with 3–4 nm wide fins and down to 20 nm designed gate length across a range of temperatures spanning from 393 K down to 4 K. Our initial results show that while our model to hardware correlation at room temperature is acceptable, at cryogenic temperatures the model may need improvement, especially in the saturation region of the device operation.