Device-, Circuit-Block-level evaluation of CFET in a 4 track library

Device-, Circuit-Block-level evaluation of CFET in a 4 track library ■

P. Schuddinck, P. Schuddinck, P. Schuddinck, O. Zografos, O. Zografos, O. Zografos, P. Weckx, P. Weckx, P. Weckx, P. Matagne, P. Matagne, P. Matagne, S. Sarkar, S. Sarkar, S. Sarkar, Y. Sherazi, Y. Sherazi, Y. Sherazi, R. Baert, R. Baert, R. Baert, D. Jang, D. Jang, D. Jang, D. Yakimets, D. Yakimets, D. Yakimets, A. Gupta, A. Gupta, A. Gupta, Bertrand Parvais, Bertrand Parvais, Bertrand Parvais, J. Ryckaert, J. Ryckaert, J. Ryckaert, D. Verkest, D. Verkest, D. Verkest, A. Mocuta, A. Mocuta, A. Mocuta

Abstract ■

The structure of the complementary FET (CFET) with NMOS stacked on top of PMOS, inherently yields standard cells and SRAM cells with 25\% smaller layout area, 25\% higher pin density and 2x higher routing flexibility than FinFET with same overall active footprint. Moreover, our work, based on advanced modelling, demonstrates that 4 track CFET can match and even outperform 5 track FinFET; without the need to lower S/D contact resistivity down to 5e-10Ωcm2 or to elevate the channel stress up to 2GPa. All gains in power-performance-area at circuit-level are maintained at block-level, making 4 track CFET a suitable candidate for N3 N2 technologies. Keywords: CFET, scaling, S/D engineering, Pi-gate.