A 150MS/s 133uW 7b ADC in 90nm digital CMOS Using a Comparator-Based Asynchronous Binary-Search sub-ADC

A 150MS/s 133uW 7b ADC in 90nm digital CMOS Using a Comparator-Based Asynchronous Binary-Search sub-ADC ■

G. Van Der Plas, Bob Verbruggen

Abstract ■

A fully dynamic 7b ADC uses a 2-step 1b-coarse 6b-fine architecture. The 6b-fine converter is implemented using a comparator-based asynchronous binary-search architecture. The prototype implementation in 90nm digital CMOS with a 1V supply achieves 6.4 ENOB and 40dB SNDR (over the whole Nyquist band) at 150MS/s, yielding a 10fJ/conversion step energy efficiency.