A 7.6 mW 1.75 GS/s 5 bit Flash A/D Converter in 90 nm Digital CMOS

A 7.6 mW 1.75 GS/s 5 bit Flash A/D Converter in 90 nm Digital CMOS ■

Bob Verbruggen, Bob Verbruggen, Bob Verbruggen, Piet Wambacq, Piet Wambacq, Piet Wambacq, Maarten Kuijk, Maarten Kuijk, Maarten Kuijk, G. Van Der Plas, G. Van Der Plas, G. Van Der Plas

Abstract ■

A 5 bit 1.75 GS/s flash ADC is realized in 90 nm CMOS. It uses a comparator array with built-in imbalance and offset calibration to lower power consumption. The SNDR is 30.9 dB at low frequencies and gradually degrades to 28.2 dB at 2 GHz. The ADC occupies 280 um by 110 um and draws only 7.6 mA from a 1 V supply yielding an energy efficiency of 0.15 pJ/conversion step.