Strain enhanced low-V T CMOS featuring La/Al-doped HfSiO/TaC and 10ps invertor delay

Strain enhanced low-V T CMOS featuring La/Al-doped HfSiO/TaC and 10ps invertor delay ■

S. Kubicek, T. Schram, E. Rohr, V. Paraschiv, R. Vos, M. Demand, C. Adelmann, T. Witters, L. Nyns, A. Delabie, L. Å Ragnarsson, T. Chiarella, C. Kerner, A. Mercha, Bertrand Parvais, M. Aoulaiche, C. Ortolland, H. Yu, A. Veloso, L. Witters, R. Singanamalla, T. Kauerauf, S. Brus, C. Vrancken, V. S. Chang, S. Z. Chang, R. Mitsuhashi, Y. Okuno, A. Akheyar, H. J. Cho, J. Hooker, B. J. O'Sullivan, S. Van Elshocht, K. De Meyer, M. Jurczak, P. Absil, S. Biesemans, T. Hoffmann

Abstract ■

We discuss several advancements over our previous report [1]: - Introduction of conventional stress boosters resulting in 16% and 11% for nMOS and pMOS respectively. For the first time the compatibility of SMT (Stress memorization technique) with High-κ/Metal Gate is demonstrated. In addition, we developed a blanket SMT process that does not require a photo to protect the pMOS by selecting a hydrogen-rich SiN film. - A comprehensive study of HfSiO and HfO2 as function of La/Al doping and spike/laser annealing. Parameters studied include Vt tuning, reliability and process control. - Demonstration of fast invertor delay of 10ps including high frequency response analysis revealing the negative impact of high metal sheet resistance and parasitic metal-poly interface oxide.