Impact of advanced process modules and device architectures on the matching performance of (sub-)45nm CMOS

Impact of advanced process modules and device architectures on the matching performance of (sub-)45nm CMOS ■

C. Gustin, A. Mercha, J. Loo, Bertrand Parvais, V. Subramaniant, M. Dehan, A. Veloso, T. Hoffmann, F. E. Leys, S. Decoutere

Abstract ■

We report for the first time a comprehensive comparison of the intra-die matching performance of most advanced multiple gate (MuGFETs) and planar bulk MOSFET technologies in terms of architectures and process modules like the gate stack and source/drain engineering. The impact of Ni-based fully silicided (FUSI) and metal (TiN and TaN) gates for bulk devices, selective epitaxial growth (SEG) and thickness of the Ni salicidation layer for MuGFETs on both threshold voltage (VT) and current factor (β) mismatch is investigated. Taking into account the device DC and matching performances, our measurements show that FUSI planar devices and MuGFETs combining selective epitaxial growth (SEG) and thin Ni salicidation are interesting candidates for applications at the 45nm node and beyond, with VT mismatch of 3.1 and 2.3 mV.μm for n-type devices, respectively.