Design and validation of an ESD protected ultra-wideband low noise amplifier is presented in this paper. It features an interstage matching network for gain roll-off compensation to achieve a flat gain over its passband. Evaluated with a chip-on-board approach, the amplifier demonstrates a gain of 11.8 ± 0.3 dB, minimum noise figure (NF) of 2.1 dB, and a group delay variation of ±30 ps from 3 to 5 GHz, even though using a less advanced 0.35-micron BiCMOS technology. Its input, output and power supply are all protected against HBM ESD stress up to 6.5 kV. Measured IIP3 at 4.5 GHz is -5.5 dBm. The core LNA draws 3 mA from a 3-V supply