A 12mW 10GHz FMCW PLL Based on an Integrating DAC with 90kHz rms Frequency Error for 23MHz/μs Slope and 1.2GHz Chirp Bandwidth

A 12mW 10GHz FMCW PLL Based on an Integrating DAC with 90kHz rms Frequency Error for 23MHz/μs Slope and 1.2GHz Chirp Bandwidth ■

Pratap Renukaswamy, Pratap Renukaswamy, Nereo Markulic, Nereo Markulic, Sehoon Park, Sehoon Park, Anirudh Kankuppe Raghavendra Swamy, Anirudh Kankuppe Raghavendra Swamy, Qixian Shi, Qixian Shi, Piet Wambacq, Piet Wambacq, Jan Craninckx, Jan Craninckx

Abstract ■

A 10GHz FMCW subsampling PLL is presented, that uses a low-power charge-integrating QDAC to tune the VCO for wideband low-noise modulation. Nonlinearities in the QDAC modulation path are corrected within 700µsec cold start-up, followed by a full on-chip background calibration engine to track supply and temperature variations. The PLL consumes 11.7mW (of which <0.5mW in the QDAC) to generate a 23.6MHz/µs chirp slope with 89kHz rms-frequency-error for 1.21GHz chirp-bandwidth.