Scaling CMOS beyond Si FinFET: An analog/RF perspective

Scaling CMOS beyond Si FinFET: An analog/RF perspective ■

Bertrand Parvais, G. Hellings, M. Simicic, P. Weckx, J. Mitard, D. Jang, V. Deshpande, B. Van Liempc, A. Veloso, A. Vandooren, N. Waldron, Piet Wambacq, Nadine Collaert, D. Verkest

Abstract ■

FinFET has been introduced in the 22/16nm node to continue CMOS logic scaling. The very tight pitches foreseen for the coming generation necessitate the introduction of different scaling boosters. In this paper, we review how these elements affect the analog device performance. The benefits of alternative channel material for dedicated RF applications and the related integration challenges are also discussed.