Process-Induced Power-Performance Variability in Sub-5-nm III

Process-Induced Power-Performance Variability in Sub-5-nm III–V Tunnel FETs

Process-Induced Power-Performance Variability in Sub-5-nm III–V Tunnel FETs ■

Yang Xiang, Yang Xiang, Anne S. Verhulst, Anne S. Verhulst, Dmitry Yakimets, Dmitry Yakimets, Bertrand Parvais, Bertrand Parvais, Anda Mocuta, Anda Mocuta, Guido Groeseneken, Guido Groeseneken

Abstract ■

We examine the power-performance variability of a projected sub-5-nm GaAsSb/InGaAs vertical tunnel FET considering various process control tolerances in the state-of-the-art device integration and propose countermeasures in device design. Nominal and three-sigma-corner device characteristics generated in quantum-mechanical/TCAD simulations are used to calibrate a semiempirical compact model, based on which the nominal and variability-inclusive energy-delay landscapes are extracted from ring-oscillator circuit simulations at sub-500-mV supply voltages. Variations in four parameters are identified as of major impact on the worst-case speed loss and iso-speed energy penalty: dopant pocket thickness, gate work function, hetero-band offset, and body thickness (in descending order). Variability-resilient device options are explored against pocket thickness variation, including: 1) pocket desensitization with increased thickness and reduced doping concentration and 2) broken-gap tunnel FET with a negative effective band gap. Reengineered devices achieve < 18 × speed loss and < 3 × energy penalty for (0.1-1) ns gate delay with respect to the nominal corner.