A DTC-Based Subsampling PLL Capable of Self-Calibrated Fractional Synthesis and Two-Point Modulation

A DTC-Based Subsampling PLL Capable of Self-Calibrated Fractional Synthesis and Two-Point Modulation ■

Nereo Markulic, Nereo Markulic, Nereo Markulic, Kuba Raczkowski, Kuba Raczkowski, Kuba Raczkowski, Ewout Martens, Ewout Martens, Ewout Martens, Pedro Emiliano Paro Filho, Pedro Emiliano Paro Filho, Pedro Emiliano Paro Filho, Benjamin Hershberg, Benjamin Hershberg, Benjamin Hershberg, Piet Wambacq, Piet Wambacq, Piet Wambacq, Jan Craninckx, Jan Craninckx, Jan Craninckx

Abstract ■

We present an analog subsampling PLL based on a digital-to-time converter (DTC), which operates with almost no performance gap (176/198 fs RMS jitter) between the integer and the worst case fractional operation, achieving -246.6 dB FOM in the worst case fractional mode. The PLL is capable of two-point, 10 Mbit/s GMSK modulation with -40.5 dB EVM around a 10.24 GHz fractional carrier. The analog nonidealities-DTC gain, DTC nonlinearity, modulating VCO bank gain, and nonlinearity-are calibrated in the background while the system operates normally. This results in \textasciitilde{}15 dB fractional spur improvement (from -41 dBc to -56.5 dBc) during synthesis and \textasciitilde{}15 dB EVM improvement (from -25 dB to -40.5 dB) during modulation. The paper provides an overview of the mechanisms that contribute to performance degradation in DTC-based PLL/phase modulators and presents ways to mitigate them. We demonstrate state-of-the-art performance in nanoscale CMOS for fractional-N synthesis and phase modulation.