A fully integrated transmitter architecture operating in the charge-domain with incremental signaling is presented. The architecture provides improved out-of-band noise performance, thanks to an intrinsic low-pass noise filtering capability, reduced quantization noise scaled by capacitance ratios, and sinc 2 alias attenuation due to a quasi-linear reconstruction interpolation. With a respective unit and baseband capacitances of 2 fF and 45 pF, the architecture attains a potential 14 bit equivalent quantization noise with a 1024 unit capacitance array. Using four 10 bit charge-based DACs (QDACs) at 128 MS/s sampling rate, it achieves -155 dBc/Hz at 45 MHz offset from a 1 GHz modulated carrier. The incremental-charge-based operation also leads to an improved efficiency at back-off conditions. For an average output power of 1 dBm (20 MHz BW), total power consumption is 41.3 mW, of which only 0.5 mW corresponds to the system charge intake. The prototype is implemented using a 28 nm 0.9 V CMOS technology, with a core area of 0.25 mm 2 . With a reduced sampling frequency and number of bits, power and area consumption are among the best and will directly benefit from future technology scaling .