Design technology co-optimization for enabling 5nm gate-all-around nanowire 6T SRAM

Design technology co-optimization for enabling 5nm gate-all-around nanowire 6T SRAM ■

Trong Huynh Bao, Trong Huynh Bao, Trong Huynh Bao, Sushil Sakhare, Sushil Sakhare, Sushil Sakhare, Julien Ryckaert, Julien Ryckaert, Julien Ryckaert, Dmitry Yakimets, Dmitry Yakimets, Dmitry Yakimets, Abdelkarim Mercha, Abdelkarim Mercha, Abdelkarim Mercha, Diederik Verkest, Diederik Verkest, Diederik Verkest, Aaron Thean, Aaron Thean, Aaron Thean, Piet Wambacq, Piet Wambacq, Piet Wambacq

Abstract ■

This paper presents a comprehensive benchmarking and co-optimization of 6T SRAM bitcells designed with 5nm vertical and lateral gate-all-around nanowire FET technology for the first time. A variety of 6T SRAM bitcells configurations combined with different device integration scenarios will be discussed. Our results show that an ultra-dense SRAM bitcell (0.01 um2) can be achieved with vertical FET architecture. The bitcell designed with vertical FET are preferably targeted for low power applications while the lateral FET-based SRAM bitcells could provide 4.5x higher in performance, but resulting in a penalty of 17x increasing in the leakage current compared to the vertical designs. A Vmin of 0.45 V could be obtained for 122 SRAM bitcells implemented with vertical devices.