A 9.2–12.7 GHz wideband fractional-N subsampling PLL in 28nm CMOS with 280fs RMS jitter

A 9.2–12.7 GHz wideband fractional-N subsampling PLL in 28nm CMOS with 280fs RMS jitter ■

Kuba Raczkowski, Kuba Raczkowski, Kuba Raczkowski, Nereo Markulic, Nereo Markulic, Nereo Markulic, Benjamin Hershberg, Benjamin Hershberg, Benjamin Hershberg, Joris Van Driessche, Joris Van Driessche, Joris Van Driessche, Jan Craninckx, Jan Craninckx, Jan Craninckx

Abstract ■

This paper describes a fractional-N subsampling PLL in 28nm CMOS. Fractional lock is achieved by using a 10bit digital-to-time converter (DTC) that generates a delayed sampling clock with minimal impact on PLL performance. Background calibration guarantees appropriate DTC gain, reducing spurs. The system achieves -38 dBc of integrated phase noise (280fs RMS jitter) at 10GHz when a worst-case fractional spur of -43 dBc is present. In-band phase noise is at the level of -104 dBc/Hz. The class-B VCO used can be tuned from 9.2 GHz to 12.7 GHz (32\%). The total power consumption of the synthesizer, including the VCO, is 13 mW from 0.9V and 1.8V supplies.