A complementary dynamic residue amplifier for a 67 dB SNDR 1.36 mW 170 MS/s pipelined SAR ADC

A complementary dynamic residue amplifier for a 67 dB SNDR 1.36 mW 170 MS/s pipelined SAR ADC ■

Badr Malki, Badr Malki, Badr Malki, Bob Verbruggen, Bob Verbruggen, Bob Verbruggen, Piet Wambacq, Piet Wambacq, Piet Wambacq, Kazuaki Deguchi, Kazuaki Deguchi, Kazuaki Deguchi, Masao Iriguchi, Masao Iriguchi, Masao Iriguchi, J. Craninckx, J. Craninckx, J. Craninckx

Abstract ■

A complementary dynamic single-stage residue amplifier for a pipelined SAR ADC is presented. It re-uses charge typically wasted during the reset phase, and hence improves efficiency by a factor 2× in this block that often dominates the fundamental noise/power trade-off of the ADC. The residue amplifier achieves 90 µVrms input noise for an energy consumption of 1.5 pJ. It is used in a 2-times interleaved 6b coarse/8b fine pipelined SAR ADC. The 40nm CMOS prototype achieves 11 ENOB at 20 MS/s while consuming 165 µW, leading to an energy per conversion step of 4 fJ. It maintains more than 10.8 ENOB at low input frequencies for a clock frequency up to 180 MS/s.