Design Technology co-optimization for N10

Design Technology co-optimization for N10 ■

Julien Ryckaert, Julien Ryckaert, Julien Ryckaert, Praveen Raghavan, Praveen Raghavan, Praveen Raghavan, R Baert, R Baert, R Baert, M Garcia Bardon, M Garcia Bardon, M Garcia Bardon, M. Dusa, M. Dusa, M. Dusa, A. Mallik, A. Mallik, A. Mallik, Sushil Sakhare, Sushil Sakhare, Sushil Sakhare, B. Vandewalle, B. Vandewalle, B. Vandewalle, Piet Wambacq, Piet Wambacq, Piet Wambacq, B. Chava, B. Chava, B. Chava, K. Croes, K. Croes, K. Croes, M. Dehan, M. Dehan, M. Dehan, D. Jang, D. Jang, D. Jang, P. Leray, P. Leray, P. Leray, T.-T. Liu, T.-T. Liu, T.-T. Liu, Kenichi Miyaguchi, Kenichi Miyaguchi, Kenichi Miyaguchi, Bertrand Parvais, Bertrand Parvais, Bertrand Parvais, P. Schuddinck, P. Schuddinck, P. Schuddinck, P. Weemaes, P. Weemaes, P. Weemaes, A. Mercha, A. Mercha, A. Mercha, J. Bömmels, J. Bömmels, J. Bömmels, N. Horiguchi, N. Horiguchi, N. Horiguchi, G. McIntyre, G. McIntyre, G. McIntyre, Aaron Thean, Aaron Thean, Aaron Thean, Z Tokei, Z Tokei, Z Tokei, S. Cheng, S. Cheng, S. Cheng, Diederik Verkest, Diederik Verkest, Diederik Verkest, A. Steegen, A. Steegen, A. Steegen

Abstract ■

Design-Technology co-optimization becomes a key knob to enable CMOS scaling. In this work we evaluate the technology options including lithography options as well as device options that are considered to enable N10 scaling by exploring their impact on representative designs such as standard cells, SRAM and analog contexts. This paper illustrates that the design angle needs to be considered early in the development of a technology node. This design assessment and decisions start from lithography constraints and options to power/performance, area and cost, all of which create the Design-Technology Co-Optimization space.