A 2.1 mW 11b 410 MS/s dynamic pipelined SAR ADC with background calibration in 28nm digital CMOS

A 2.1 mW 11b 410 MS/s dynamic pipelined SAR ADC with background calibration in 28nm digital CMOS ■

A. Verbruggen, Masao Iriguchi, Manuel De La Guia Solaz, Guy Glorieux, Kazuaki Deguchi, Badr Malki, J. Craninckx

Abstract ■

A 410 MS/s 2x interleaved 11bit pipelined SAR ADC in 28nm digital CMOS is presented. Each ADC channel consists of a 6b coarse SAR, a dynamic residue amplifier and a 7b fine SAR and includes an on-chip calibration engine that detects and corrects comparator offsets and amplifier gain errors in the background. The ADC achieves a peak SNDR of 59.8 dB at 410 MS/s for an energy per conversion step of 6.5 fJ.