This paper presents an inductorless static 2:1 frequency divider operating up to 60 GHz. In order to save the chip area no peaking inductors are used in this design. Alternatively, to achieve the high operating frequency, the range is extended by asymmetrical sizing of the data and latch transistors and by reducing the load of the following buffer stage. The load reduction is achieved by means of a gate-drain capacitance neutralization in the following differential buffer stage. The circuit is realized in a 28 nm CMOS technology. Measurements show that the divider exhibits a maximum operating frequency of 60 GHz and features an input sensitivity below 0 dBm over a broad input frequency range of 34 GHz. The divider core consumes 7.3 mA from a single 0.9 V supply.