This paper investigates the impact of redundancy on electromigration (EM) risk in unit cells derived from power delivery networks (PDN) in advanced technology nodes. Test structures were fabricated in a commercial 28-nm technology node with minimum feature sizes of 45 nm. For the first time, activation energy was extracted for PDN tiles composed of different metal dimensions, showing that it can vary depending on the adopted failure criterion and is related to the metallization layers present in the stack. Linewidth scaling worsens shunting effect, as void incubation in advanced nodes tends to produce near-open failures with a sharp resistance increase (\textasciitilde{}0.4 kΩ for 45 nm lines). Nevertheless, the presence of redundant current paths can partially mitigate this effect by allowing current redistribution, delaying functional degradation. Further, in this study, a new chip level reliability assessment methodology is proposed that considers available IR-drop margins rather than relying on the conventional resistance-change failure criterion, which is overly conservative and significantly impacts the reliability margin of PDN tiles. Finally, a three-dimensional TCAD simulator was calibrated with single line experiments and employed to validate experimental trends.