High-Speed and High-Resolution Delta Sigma Analog to Digital Converters for 5G Applications 

The recent development of 5G communication came with astringent analog-to-digital conversion requirements such as 80dB Dynamic Range and up to 100MHz bandwidth with minimal power consumption. Those specifications are on par with the what is achieved by the state-of-the-art ADCs in the most recent publications. The improvement of converters is being slowed down by the reduced intrinsic gain in smaller technology nodes of CMOS process (sub-65nm).

To leverage the speed advantages of a 28nm process with limited intrinsic gain, this research is exploring the usage of ring amplifiers in the delta sigma architecture to reach the 5G specification. Ring amplifiers are known for scaling well with technology process and still achieving medium range gain necessary for the implementation of noise shaping in Delta Sigma architectures. To the best of the authors knowledge, no ring amplifier based Delta Sigma ADC was published in such advanced node and this work could push the boundaries of figure of merit of Discrete Time Delta Sigma to the high bandwidth domain.