Integrated radio front-end circuits of wireless applications for 5G and beyond 

In today’s world, wireless communication is playing an important role. Users of smartphones, tablets, laptops, and smartwatches use wireless communication for part of their social life, to follow the news, to virtually attend a meeting e.g. while commuting, to find their way, … and the expectation is that in the future even more people will do that. This will give rise to strong growth of data that is transported in a wireless fashion. Most of the data will consist of high-definition video and transport of data will happen with very low latencies. The fifth generation (5G) of wireless communication is about to come, with deployment starting in 2020. The 5G standard will provide peak data rates of 10 gigabits per second (Gbps). Beyond the 5G era, the demand for higher data rates will not stop. This Ph.D. targets the design of these challenging high-capability circuits for wireless communication systems of 5G and beyond. For applications for wireless communication, where a mass market is expected. These works can be potentially commercialized for 5G and beyond infrastructure or user end.

A Ph.D. in collaboration with imec 

This Ph.D. focuses on the design of circuits for wireless communication systems at high data rates up to 100 Gbps. The circuits that will be considered in this Ph.D. are the so-called front-end circuits that operate at the millimeter-wave (mmW) frequency and that are closest to the antenna of the transmit and receive parts. In the transmit part, the circuit that will be considered first is the power amplifier (PA), after which phase shifting will be implemented. For the receiver, the low-noise amplifier (LNA) will be considered first and then phase shifting will be addressed. Next, the design of frequency conversion circuitry (up-conversion in the transmit path, down-conversion in the receive path) will be considered. From all mmW building blocks discussed above, the power amplifier is generally the most critical one for two reasons: for a given IC technology, the capability to generate RF power goes down when operating frequency goes up, and the power amplifier mostly dominates the power consumption of the analog part of a communication transceiver. For this reason, most attention will be paid to the design of power amplifiers. The required transmit power will be determined based on a link budget analysis of a communication system that will be elaborated at the very beginning of the thesis. For the power amplifier, it will be investigated if efficiency and output power can be increased in comparison to a simple Class-AB stage. Further, gain-boosting techniques of PA should be explored to overcome the limited fmax of the adopted silicon processes at such a high operation frequency. In addition, the passive components to be designed as distributed elements or lumped elements need to be investigated, and layout parasitics will require careful modeling.

Achievements (Honors & Awards) 
  • IEEE RFIC2021 Best Student Paper Finalists
  • IEEE NEWCAS2019 Best Paper Award
  • IEEE Student Member