Thean, AV.-Y., Yakimets, D., Huynh, B. T., Schuddinck, P., Sakhare, S., Bardon, M. G., Sibaja-Hernandez, A., Ciofi, I., Eneman, G., Veloso, A., Ryckaert, J., Raghavan, P., Mercha, A., Tokei, Z., Verkest, D., Wambacq, P., De Meyer, K., & Collaert, N. (2015). Vertical device architecture for 5nm and beyond: device & circuit implications. In 2015 Symposium on VLSI Technology and Circuits (pp. 26-27). Article T26 IEEE. https://doi.org/10.1109/VLSIT.2015.7223689

@inproceedings{5cd2115cdc984e87b1df4620dc0dd689,
title = "Vertical device architecture for 5nm and beyond: device & circuit implications",
abstract = "Vertical nanowire logic circuits may enable device density scaling well beyond lateral CMOS layouts limited by gate and contact placement. In this paper, we compared the performance, layout efficiency, SRAM design, and parasitics between vertical (VFETs) gate-all-around (GAA) transistors with lateral (LFETs) targeting 5nm. We reviewed some of the unique considerations of VFET device and circuit influences.",
author = "AV-Y Thean and Dimitri Yakimets and Huynh, {Bao Trong} and P. Schuddinck and Sushil Sakhare and Bardon, {M Garcia} and A. Sibaja-Hernandez and I Ciofi and G. Eneman and A Veloso and Julien Ryckaert and Praveen Raghavan and A. Mercha and Z Tokei and Diederik Verkest and Piet Wambacq and {De Meyer}, Kurt and Nadine Collaert",
year = "2015",
doi = "10.1109/VLSIT.2015.7223689",
language = "English",
pages = "26--27",
booktitle = "2015 Symposium on VLSI Technology and Circuits",
publisher = "IEEE",
note = "2015 Symposium on VLSI Technology and Circuits ; Conference date: 15-06-2015 Through 19-06-2015",
url = "http://www.vlsisymposium.org/Past/15web/",
}