This paper presents a charge-domain SAR ADC which integrates the current of a variable-gain transconductor on its sampling capacitor, rather than being driven by a power hungry voltage buffer. The sampling circuit uses nonlinear MOS capacitors for passive amplification, without compromising linearity. The prototype in 40nm LP CMOS consists of a 1.1-17.6mS transconductor, combined with a 10b 0-80MS/s charge-sharing SAR ADC. It achieves 70 dB DR while consuming less than 5.45mA from a 1.1V supply.
Malki, B, Yamamoto, T, Verbruggen, B, Wambacq, P & Craninckx, J 2012, A 70dB DR 10b 0-to-80MS/s current-integrating SAR ADC with adaptive dynamic range. in 2012 IEEE International Solid-State Circuits Conference: Digest of technical papers. Digest of Technical Papers - IEEE International Solid-State Circuits Conference, vol. 55, IEEE, St. Louis, Missouri, pp. 470-471, 2012 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, United States, 19/02/12. <http://ieeexplore.ieee.org/xpl/articleDetails.jsp?reload=true&arnumber=6177095>
Malki, B., Yamamoto, T., Verbruggen, B., Wambacq, P., & Craninckx, J. (2012). A 70dB DR 10b 0-to-80MS/s current-integrating SAR ADC with adaptive dynamic range. In 2012 IEEE International Solid-State Circuits Conference: Digest of technical papers (pp. 470-471). (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 55). IEEE. http://ieeexplore.ieee.org/xpl/articleDetails.jsp?reload=true&arnumber=6177095
@inproceedings{b1339896ebcf43a0ad05b27a7d6f9b0b,
title = "A 70dB DR 10b 0-to-80MS/s current-integrating SAR ADC with adaptive dynamic range",
abstract = "This paper presents a charge-domain SAR ADC which integrates the current of a variable-gain transconductor on its sampling capacitor, rather than being driven by a power hungry voltage buffer. The sampling circuit uses nonlinear MOS capacitors for passive amplification, without compromising linearity. The prototype in 40nm LP CMOS consists of a 1.1-17.6mS transconductor, combined with a 10b 0-80MS/s charge-sharing SAR ADC. It achieves 70 dB DR while consuming less than 5.45mA from a 1.1V supply.",
keywords = "ADC VGA Tranisotor capacitance amplification DAC, Comparator fully dynamic SNDR SFDR",
author = "Badr Malki and Takaya Yamamoto and Bob Verbruggen and Piet Wambacq and J. Craninckx",
year = "2012",
month = feb,
day = "19",
language = "English",
isbn = "978-1-4673-0373-6",
series = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",
publisher = "IEEE",
pages = "470--471",
booktitle = "2012 IEEE International Solid-State Circuits Conference",
note = "2012 IEEE International Solid-State Circuits Conference (ISSCC) ; Conference date: 19-02-2012 Through 23-02-2012",
}