With the increasing cost of scaled CMOS, effort is spent in maximizing performance attainable in already available technologies. Above-IC technology (A-IC), consisting of a 5 ? m thick electroplated Cu layer on an 18 micron low-K BCB dielectric, post-processed on top of the CMOS, provides a low-cost solution to achieve high-Q passive devices, with relaxed mask requirements. A technique is presented to fully layout a VCO under its A-IC inductor, by using a two-layer shield in the top layers of the CMOS back-end, enabling 3D integration of active circuitry and high-Q passives. The technique is demonstrated on an LC-VCO in 45nm bulk CMOS, that consumes only 400 ? W, and occupies a low area of 0.12mm2.
Borremans, J, Wambacq, P, Kuijk, M, Carchon, G & Decoutere, S 2008, A 400uW, 4.7-6.4GHz VCO under an Above-IC inductor in 45nm CMOS. in International Solid-State Circuits Conference (ISSCC). IEEE, pp. 536-537, Finds and Results from the Swedish Cyprus Expedition: A Gender Perspective at the Medelhavsmuseet, Stockholm, Sweden, 21/09/09.
Borremans, J., Wambacq, P., Kuijk, M., Carchon, G., & Decoutere, S. (2008). A 400uW, 4.7-6.4GHz VCO under an Above-IC inductor in 45nm CMOS. In International Solid-State Circuits Conference (ISSCC) (pp. 536-537). IEEE.
@inproceedings{40a94aea887240e5a2c0ea332466e9fa,
title = "A 400uW, 4.7-6.4GHz VCO under an Above-IC inductor in 45nm CMOS",
abstract = "With the increasing cost of scaled CMOS, effort is spent in maximizing performance attainable in already available technologies. Above-IC technology (A-IC), consisting of a 5 ? m thick electroplated Cu layer on an 18 micron low-K BCB dielectric, post-processed on top of the CMOS, provides a low-cost solution to achieve high-Q passive devices, with relaxed mask requirements. A technique is presented to fully layout a VCO under its A-IC inductor, by using a two-layer shield in the top layers of the CMOS back-end, enabling 3D integration of active circuitry and high-Q passives. The technique is demonstrated on an LC-VCO in 45nm bulk CMOS, that consumes only 400 ? W, and occupies a low area of 0.12mm2.",
keywords = "CMOS, 45 nm, VCO, Above IC",
author = "Jonathan Borremans and Piet Wambacq and Maarten Kuijk and Geert Carchon and S. Decoutere",
year = "2008",
month = feb,
day = "3",
language = "English",
isbn = "978-1-4244-2010-0",
pages = "536--537",
booktitle = "International Solid-State Circuits Conference (ISSCC)",
publisher = "IEEE",
note = "Finds and Results from the Swedish Cyprus Expedition: A Gender Perspective at the Medelhavsmuseet ; Conference date: 21-09-2009 Through 25-09-2009",
}