Scheir, K., Bronckers, S., Borremans, J., Wambacq, P., & Rolain, Y. (2008). A 52 GHz Phased-Array Receiver Front-End in 90nm Digital CMOS. In 2008 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) IEEE.

@inproceedings{b4814531e5f14571a730fabb49bc1701,
title = "A 52 GHz Phased-Array Receiver Front-End in 90nm Digital CMOS",
abstract = "A 52GHz phased-array homodyne receiver front-end with 2 antenna paths is implemented in 90nm digital CMOS. The QVCO and phase selectors provide control over the phase of the LO-signals, allowing beamforming and steering. The receiver achieves a conversion gain of 30dB/path and an NF of 7.1dB/path, yielding a system NF of 4.1dB. The chip consumes 65mW and occupies 0.1mm2.",
keywords = "60GHz, calibration, CMOS, mm-wave, phased-array, QVCO, tuning range, variable gain",
author = "Karen Scheir and Stephane Bronckers and Jonathan Borremans and Piet Wambacq and Yves Rolain",
year = "2008",
month = feb,
day = "3",
language = "English",
isbn = "978-1-4244-2010-0",
booktitle = "2008 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)",
publisher = "IEEE",
note = "2008 IEEE International Solid-State Circuits Conference (ISSCC), ISSCC ; Conference date: 03-02-2008 Through 07-02-2008",
url = "http://www.isscc.org",
}