A 57-to-66GHz quadrature PLL in low-power 45nm digital CMOS achieves a large tuning range with 2 QVCOs and a tunable injection-locked prescaler. The circuit has quadrature outputs, consumes 78mW from a 1.1V supply, achieves a phase noise of -82dBc/Hz at 3MHz offset around 61.6GHz, and has a reference spur level of -42dBc.
Scheir, K, Vandersteen, G, Rolain, Y & Wambacq, P 2009, A 57-to-66GHz Quadrature PLL in 45nm Digital CMOS. in 2009 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE, ISSCC 09, USA, San Francisco, February 8-12, 2009. Finds and Results from the Swedish Cyprus Expedition: A Gender Perspective at the Medelhavsmuseet, Stockholm, Sweden, 21/09/09.
Scheir, K., Vandersteen, G., Rolain, Y., & Wambacq, P. (2009). A 57-to-66GHz Quadrature PLL in 45nm Digital CMOS. In 2009 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE, ISSCC 09, USA, San Francisco, February 8-12, 2009
@inproceedings{76f5e92811574292a7abf37532824367,
title = "A 57-to-66GHz Quadrature PLL in 45nm Digital CMOS",
abstract = "A 57-to-66GHz quadrature PLL in low-power 45nm digital CMOS achieves a large tuning range with 2 QVCOs and a tunable injection-locked prescaler. The circuit has quadrature outputs, consumes 78mW from a 1.1V supply, achieves a phase noise of -82dBc/Hz at 3MHz offset around 61.6GHz, and has a reference spur level of -42dBc.",
keywords = "circuits, Digital CMOS",
author = "Karen Scheir and Gerd Vandersteen and Yves Rolain and Piet Wambacq",
year = "2009",
month = feb,
day = "8",
language = "English",
booktitle = "2009 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE, ISSCC 09, USA, San Francisco, February 8-12, 2009",
note = "Finds and Results from the Swedish Cyprus Expedition: A Gender Perspective at the Medelhavsmuseet ; Conference date: 21-09-2009 Through 25-09-2009",
}