Wambacq, P., Mercha, A., Scheir, K., Verbruggen, B., Borremans, J., De Heyn, V., Thijs, S., Linten, D., Van Der Plas, G., Parvais, B., Dehan, M., Decoutere, S., Soens, C., Collaert, N., & Jurczak, M. (2008). Advanced planar bulk and multigate CMOS technology: analog-circuit benchmarking up to mm-wave frequencies. In ISSCC 2008, Solid-State Circuits Conference, San Francisco, CA, 3-7 February 2008 (pp. 528-529). IEEE.

@inproceedings{9362174df7364e3b9b514b9b9c1f1015,
title = "Advanced planar bulk and multigate CMOS technology: analog-circuit benchmarking up to mm-wave frequencies",
abstract = "CMOS scaling beyond 45nm requires devices that deviate from the planar bulk transistor with a polysilicon gate and nitrided silicon dioxide (SiON) as gate dielectric. To downscale planar bulk devices, strain is used to boost mobility and new materials are introduced in the gate stack. Multigate devices such as fully-depleted SOI FinFETs (Fig. 29.4.1) are also candidates for downscaling beyond 45nm.",
keywords = "CMOS",
author = "Piet Wambacq and Abdelkarim Mercha and Karen Scheir and Bob Verbruggen and Jonathan Borremans and {De Heyn}, Vincent and Steven Thijs and Dimitri Linten and {Van Der Plas}, Geert and Bertrand Parvais and Morin Dehan and S. Decoutere and Charlotte Soens and Nadine Collaert and M. Jurczak",
year = "2008",
language = "English",
isbn = "978-1-4244-2010-0",
pages = "528--529",
booktitle = "ISSCC 2008, Solid-State Circuits Conference, San Francisco, CA, 3-7 February 2008",
publisher = "IEEE",
note = "Finds and Results from the Swedish Cyprus Expedition: A Gender Perspective at the Medelhavsmuseet ; Conference date: 21-09-2009 Through 25-09-2009",
}