Publication Details
Y. Xiang, S. Tyaginov, M. Vandemaele, Z. Wu, J. Franco, E. Bury, B. Truijen, Bertrand Parvais, D. Linten, B. Kaczer

2021 IEEE International Reliability Physics Symposium, IRPS 2021 - Proceedings

Contribution To Book Anthology


The continued challenge of front-end-of-line transistor reliability has long demanded physics-based SPICE compact models, not only for service lifetime estimation, but also for aging-aware device pathfinding with technology scaling and innovation. Here, we present a predictive hot-carrier-degradation (HCD) compact model built upon the industry-standard BSIM model, that conveniently embeds the essential HCD physics within common SPICE simulation flows. We leverage and augment the established, scalable electrostatics and transport in BSIM as the input to an analytical HCD interface states generation formalism, the result of which is in turn injected back into BSIM for a self-consistent estimation of the threshold voltage (VTH) shift and the mobility degradation. Our approach readily exhibits fundamental, non-empirical predictabilities of the stress time-and the sensing bias-dependency of transistor-level degradation, without having to resort to a priori assumptions. This will further accommodate the irregular, arbitrary voltage waveforms in transient circuit operations, thus enabling efficient evaluation of the power-performance degradation at circuit level. The model ultimately aims to lay the groundwork for a reliability-aware design-technology co-optimization in device pathfinding.

DOI scopus