Publication Details
Zhiwei Zong



The use of spectrum in the millimeter-wave (mm-Wave) frequency range is considered as a key enabler to continue the insatiable demand for increased wireless data capacity. This spectrum will be adopted in the 5G wireless communication standard. To obtain a high integration degree for the implementation of 5G mm-Wave transceivers, advanced CMOS is the preferred technology. The higher operating frequency, compared to 4G, poses more design challenges on the key building blocks of a transceiver. This PhD thesis focuses on the design of the two key building blocks in a 5G mm-Wave transceiver, namely a voltage-controlled oscillator (VCO) and a power amplifier (PA). All building blocks designed in this PhD work are operating in the 20-30 GHz frequency region. All building blocks have been designed in a 22nm fully-depleted silicon-on-insulator (FD-SOI) CMOS technology. First, a modified transformer-feedback VCO (TF-VCO) with a sourcebridging capacitor (Cs) is introduced. Thanks to the use of Cs, the phase noise (PN) in the 1/f2 and 1/f3 regions are both improved compared to earlier published TF-VCOs. The origin of the PN improvement by the use Cs is explained in this thesis. It is seen that with Cs we can improve the symmetry of the waveform of the voltage over the tank of the VCO. Also, with Cs the effective quality factor of the transformer can be increased, which also reduces phase noise. These theoretical investigations are proven with measurement results. With a second design, an LC-VCO design, another key design challenge is tackled, namely the suppression of flicker noise upconversion. A 22-29GHz voltage-biased LC-VCO is designed and implemented to suppress this flicker noise upconversion by using a flicker noise filtering technique. A self-coupled inductor and a common-centroid capacitor bank layout are proposed in this design to guarantee a good flicker noise suppression over the frequency tuning range. Next, two 28GHz PAs are designed and implemented for 5G mm-Wave communications. The first PA focuses on generation of a high output power (Pout) with a high linearity. This is achieved in a first design that uses a two-way current combiner and an output stage that uses stacking of transistors. The stack of three transistors used in this design enables the generation of a high output power without overstressing the core devices. The second PA focuses on the power back-off (PBO) efficiency enhancement. This is important for communication with a high spectral efficiency: high-order modulation requires to operate at a relatively large back-off from the saturation level. The design is based on the Doherty architecture. By merging lumped passive components into a transformer, a transformer-based Doherty PA with a compact power combiner is obtained, achieving Doherty load modulation with a compact footprint. This design has the highest power density and ITRS PA figure-of-merit (FOM) among the published mm-wave Doherty PAs.