Publication Details



Frequency-Modulated Continuous-Wave (FMCW) radar sensors are gaining popularity in the area of contactless range and velocity tracking for indoor localization applications like vital signs monitoring and gesture recognition. FMCW radars for such short range sensing systems are particularly interesting because of high range resolution, non-sensitivity to ambient lighting conditions and low probability of interception. At the heart of the sensor lies the chirp synthesizer, which is typically implemented by using a Phase-Locked Loop (PLL). The radar performance depends on the linearity and phase noise performance of the chirp generated. Further, the power consumption of the chirp synthesizer needs to be optimized for sensor integration on smart devices and other battery-powered applications. A fast sawtooth chirp with high chirp slope needs to be synthesized to increase simultaneous velocity and range separation and improve target SNR in a low-cost CMOS technology. To address these challenges, this thesis presents the PLL modulation architecture and circuit blocks for low-power and high-performance chirp synthesis, and its verification using two 28 nm bulk CMOS prototype Integrated Circuits (ICs). In the first design a 10 GHz sub-sampling PLL in a Two-Point Modulation (TPM) architecture is implemented for chirp synthesis. To enable frequency modulation while maintaining a low-noise over a wideband, a low-power Charge-Integrating Digital-to Analog Converter (QDAC) is introduced in the high-pass injection path. The nonlinearities present in the QDAC modulation path are compensated by using a background calibration engine. The synthesizer consumes 11.7 mW of power to generate a 23.6 MHz/µs chirp-slope with 28 kHz rms-frequency-error for 1.21 GHz chirp-bandwidth. The second prototype introduces a duty-cycling scheme to reduce the overall power consumption. To enable fast startup and fast locking, a two-point modulated Charge Pump (CP)-PLL frequency modulator is designed. To enable the two-point gain mismatch calibration a time domain sign extraction technique is explored. The 16 GHz chirp generator achieves a 29.3 MHz/µs chirp-slope with 41 kHz rms-frequency-error for 1.5 GHz chirp-bandwidth while consuming 16.5 mW power, which can be heavily duty-cycled without significant overhead in the PLL locking time.