Mohamed Naeim, Mohamed Naeim, Herman Oprins, Herman Oprins, Sudipta Das, Sudipta Das, Geert Van Der Plas, Geert Van Der Plas, Yun Dai, Yun Dai, Pinhong Chen, Pinhong Chen, C. T. Kao, C. T. Kao, Dwaipayan Biswas, Dwaipayan Biswas, Dragomir Milojevic, Dragomir Milojevic
Thermal challenges in 3D-IC arise from the high thermal resistance of the 3D interface layer and Back-End-Of-Line (BEOL), leading to poor heat dissipation \& increased peak junction temperature. In this study we analyze the impact of technology and material parameters of Embedded micro-Bumps (E-μ Bumps) and Wafer-to- Wafer (W2W)-Hybrid Bonding (HB) on thermal behaviour of the package stack. Thermal analysis is conducted on a 64-core SoC with power density of 140\textbackslash{} W/cm2 using advanced A14 nanosheet CMOS technology. Simulation outcomes demonstrate that as the amount of metal in the 3D interface increases (relative to dielectric) from 0\% to 20\%, the peak temperature Tmax of E-μ Bumps decreases by 20\%, beyond which Tmax is limited by the BEOL thermal resistance. The study demonstrates that at 20\% metal density, the thermal impact of stand-off height is negligible, regardless of 3D interface technology. Among 2-die stacks, Memory-on-Logic (MoL) configuration exhibits the highest Tmax, 5°C above the 2D baseline, while 3-tier stack increase Tmax by 12°C, necessitating an extra 33\% heat transfer efficiency to reduce Tmax. Additionally, for BEOL analysis, introducing backside PDN, results in 2°C increase for 2D and 2°C reduction for 3D (MoL) configurations.
Naeim, M, Oprins, H, Das, S, Van Der Plas, G, Dai, Y, Chen, P, Kao, CT, Biswas, D & Milojevic, D 2024, 'Thermal Analysis of 3D Stacking and BEOL Technologies with Functional Partitioning of Many-Core RISC-V SoC', Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI, pp. 33-38. https://doi.org/10.1109/ISVLSI61997.2024.00018
Naeim, M., Oprins, H., Das, S., Van Der Plas, G., Dai, Y., Chen, P., Kao, C. T., Biswas, D., & Milojevic, D. (2024). Thermal Analysis of 3D Stacking and BEOL Technologies with Functional Partitioning of Many-Core RISC-V SoC. Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI, 33-38. https://doi.org/10.1109/ISVLSI61997.2024.00018
@article{bda688fb0f8040cdbab9ead0d768b262,
title = "Thermal Analysis of 3D Stacking and BEOL Technologies with Functional Partitioning of Many-Core RISC-V SoC",
abstract = "Thermal challenges in 3D-IC arise from the high thermal resistance of the 3D interface layer and Back-End-Of-Line (BEOL), leading to poor heat dissipation \& increased peak junction temperature. In this study we analyze the impact of technology and material parameters of Embedded micro-Bumps (E-μ Bumps) and Wafer-to- Wafer (W2W)-Hybrid Bonding (HB) on thermal behaviour of the package stack. Thermal analysis is conducted on a 64-core SoC with power density of 140\textbackslash{} W/cm2 using advanced A14 nanosheet CMOS technology. Simulation outcomes demonstrate that as the amount of metal in the 3D interface increases (relative to dielectric) from 0\% to 20\%, the peak temperature Tmax of E-μ Bumps decreases by 20\%, beyond which Tmax is limited by the BEOL thermal resistance. The study demonstrates that at 20\% metal density, the thermal impact of stand-off height is negligible, regardless of 3D interface technology. Among 2-die stacks, Memory-on-Logic (MoL) configuration exhibits the highest Tmax, 5°C above the 2D baseline, while 3-tier stack increase Tmax by 12°C, necessitating an extra 33\% heat transfer efficiency to reduce Tmax. Additionally, for BEOL analysis, introducing backside PDN, results in 2°C increase for 2D and 2°C reduction for 3D (MoL) configurations.",
keywords = "3D partitioning, 3D-IC, logic-on-logic, logic-on-memory, memory-on-logic, multi-tiers, Thermal analysis",
author = "Mohamed Naeim and Herman Oprins and Sudipta Das and \{Van Der Plas\}, Geert and Yun Dai and Pinhong Chen and Kao, \{C. T.\} and Dwaipayan Biswas and Dragomir Milojevic",
note = "Publisher Copyright: {\textcopyright} 2024 IEEE.; 2024 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2024 ; Conference date: 01-07-2024 Through 03-07-2024",
year = "2024",
month = sep,
day = "25",
doi = "10.1109/ISVLSI61997.2024.00018",
language = "English",
pages = "33--38",
journal = "Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI",
issn = "2159-3469",
}