This paper presents a methodology to help prevent overdesign of Electrostatic Discharge (ESD) protection circuits for internal I/O in 2.5D/3D bonding technologies. We explore how the voltage suppression effect mitigates voltage-driven gate oxide breakdown during stacking and emphasize the role of series resistance in reducing peak discharge current. Our findings indicate that highly variable non-contact discharges are not a concern in advanced bonding technologies, shifting the focus to more predictable contact discharges. Also, we provide guidelines to design efficient ESD protection circuits for internal IO in 2.5D/3D stacked system.
Lin, S-H, Simicic, M, Pantano, N, Chen, S-H, Van Der Plas, G, Beyne, E & Wambacq, P 2024, Toward 0 V ESD Protection in 2.5D/3D Advanced Bonding Technology. in 2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits). Digest of technical papers - Symposium on VLSI Technology, IEEE, Honolulu, HI, USA, pp. 1-2. https://doi.org/10.1109/VLSlTechnologyandCir46783.2024.10631467, https://doi.org/10.1109/VLSITechnologyandCir46783.2024.10631467
Lin, S.-H., Simicic, M., Pantano, N., Chen, S.-H., Van Der Plas, G., Beyne, E., & Wambacq, P. (2024). Toward 0 V ESD Protection in 2.5D/3D Advanced Bonding Technology. In 2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) (pp. 1-2). (Digest of technical papers - Symposium on VLSI Technology). IEEE. https://doi.org/10.1109/VLSlTechnologyandCir46783.2024.10631467, https://doi.org/10.1109/VLSITechnologyandCir46783.2024.10631467
@inproceedings{38b88dea69a543fdac88a580df10c171,
title = "Toward 0 V ESD Protection in 2.5D/3D Advanced Bonding Technology",
abstract = "This paper presents a methodology to help prevent overdesign of Electrostatic Discharge (ESD) protection circuits for internal I/O in 2.5D/3D bonding technologies. We explore how the voltage suppression effect mitigates voltage-driven gate oxide breakdown during stacking and emphasize the role of series resistance in reducing peak discharge current. Our findings indicate that highly variable non-contact discharges are not a concern in advanced bonding technologies, shifting the focus to more predictable contact discharges. Also, we provide guidelines to design efficient ESD protection circuits for internal IO in 2.5D/3D stacked system. ",
author = "Shih-Hsiang Lin and Marko Simicic and Nicolas Pantano and Shih-Hung Chen and \{Van Der Plas\}, Geert and Eric Beyne and Piet Wambacq",
year = "2024",
month = jun,
day = "6",
doi = "10.1109/VLSlTechnologyandCir46783.2024.10631467",
language = "English",
isbn = "979-8-3503-6147-6",
series = "Digest of technical papers - Symposium on VLSI Technology",
publisher = "IEEE",
pages = "1--2",
booktitle = "2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)",
}