Das, S., Kumari, B., Sahoo, S. S., Chen, Y., Myers, J., Milojevic, D., Biswas, D., & Ryckaert, J. (2024). Toward Fine-Grained Partitioning of Low-Level SRAM Caches for Emerging 3D-IC Designs. IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, 10, 67-74. https://doi.org/10.1109/JXCDC.2024.3468386

@article{e37cefdef69a4693b2a9a1470070ad65,
title = "Toward Fine-Grained Partitioning of Low-Level SRAM Caches for Emerging 3D-IC Designs",
abstract = "Scaling on-chip memory capacity is one of the primary approaches to mitigate memory wall bottlenecks. Various 2.5-D/3-D integration schemes, leveraging novel partitioning, are being actively explored to improve system performance. However, fine-grained functional partitioning of memory macros is not widely reported. As static RAM (SRAM) scaling stagnates with emerging CMOS logic roadmap, we propose a partitioning of low-level (faster access) caches in 3-D using an array under CMOS (AuC) technology paradigm. Our study focuses on partitioning and optimization of SRAM bit-cells and peripheral circuits, enabling heterogeneous integration, achieving up to 12\% higher operating frequency with 50\% leakage power reduction in the memory macros. Applied on a 64-bit mobile system-on-chip (SoC) CPU core, we achieve up to 60\% higher energy efficiency compared with 2-D baseline and 14\% increase in operating frequency compared with standard memory-on-logic 3-D partitioning scheme.",
keywords = "3DIC, ARM, AuC, SRAM",
author = "Sudipta Das and Bhawana Kumari and Sahoo, \{Siva Satyendra\} and Yukai Chen and James Myers and Dragomir Milojevic and Dwaipayan Biswas and Julien Ryckaert",
note = "Publisher Copyright: {\textcopyright} 2024 The Authors.",
year = "2024",
month = sep,
day = "26",
doi = "10.1109/JXCDC.2024.3468386",
language = "English",
volume = "10",
pages = "67--74",
journal = "IEEE Journal on Exploratory Solid-State Computational Devices and Circuits",
issn = "2329-9231",
publisher = "IEEE",
}