Van Der Plas, G., & Verbruggen, B. (2008). A 150MS/s 133uW 7b ADC in 90nm digital CMOS Using a Comparator-Based Asynchronous Binary-Search sub-ADC. In 2008 IEEE International Solid-State Circuits Conference: Digest of Technical Papers (pp. 242-243). (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 51). IEEE.

@inproceedings{b9f4057ff2254e3d82da574715a0a3c1,
title = "A 150MS/s 133uW 7b ADC in 90nm digital CMOS Using a Comparator-Based Asynchronous Binary-Search sub-ADC",
abstract = "A fully dynamic 7b ADC uses a 2-step 1b-coarse 6b-fine architecture. The 6b-fine converter is implemented using a comparator-based asynchronous binary-search architecture. The prototype implementation in 90nm digital CMOS with a 1V supply achieves 6.4 ENOB and 40dB SNDR (over the whole Nyquist band) at 150MS/s, yielding a 10fJ/conversion step energy efficiency.",
keywords = "ADC, high efficiency",
author = "{Van Der Plas}, G. and Bob Verbruggen",
year = "2008",
month = feb,
day = "3",
language = "English",
isbn = "978-1-4244-2010-0",
series = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",
publisher = "IEEE",
pages = "242--243",
booktitle = "2008 IEEE International Solid-State Circuits Conference",
note = "2008 IEEE International Solid-State Circuits Conference (ISSCC), ISSCC ; Conference date: 03-02-2008 Through 07-02-2008",
url = "http://www.isscc.org",
}