Verbruggen, B., Wambacq, P., Kuijk, M., & Van Der Plas, G. (2008). A 7.6 mW 1.75 GS/s 5 bit Flash A/D Converter in 90 nm Digital CMOS. In 2008 Symposium on VLSI Circuits Digest of Technical Papers (pp. 14-15). IEEE Solid-State Circuits Soc; Japan Soc Appl Phys.

@inproceedings{767436b737614c9daa2403a9843fb856,
title = "A 7.6 mW 1.75 GS/s 5 bit Flash A/D Converter in 90 nm Digital CMOS",
abstract = "A 5 bit 1.75 GS/s flash ADC is realized in 90 nm CMOS. It uses a comparator array with built-in imbalance and offset calibration to lower power consumption. The SNDR is 30.9 dB at low frequencies and gradually degrades to 28.2 dB at 2 GHz. The ADC occupies 280 um by 110 um and draws only 7.6 mA from a 1 V supply yielding an energy efficiency of 0.15 pJ/conversion step.",
keywords = "ADC, high speed",
author = "Bob Verbruggen and Piet Wambacq and Maarten Kuijk and {Van Der Plas}, G.",
year = "2008",
month = jun,
day = "18",
language = "English",
isbn = "978-1-4244-1804-6",
pages = "14--15",
booktitle = "2008 Symposium on VLSI Circuits Digest of Technical Papers",
publisher = "IEEE Solid-State Circuits Soc; Japan Soc Appl Phys",
note = "Finds and Results from the Swedish Cyprus Expedition: A Gender Perspective at the Medelhavsmuseet ; Conference date: 21-09-2009 Through 25-09-2009",
}