S. Kubicek, T. Schram, E. Rohr, V. Paraschiv, R. Vos, M. Demand, C. Adelmann, T. Witters, L. Nyns, A. Delabie, L. Ã… Ragnarsson, T. Chiarella, C. Kerner, A. Mercha,
Bertrand Parvais, M. Aoulaiche, C. Ortolland, H. Yu, A. Veloso, L. Witters, R. Singanamalla, T. Kauerauf, S. Brus, C. Vrancken, V. S. Chang, S. Z. Chang, R. Mitsuhashi, Y. Okuno, A. Akheyar, H. J. Cho, J. Hooker, B. J. O'Sullivan, S. Van Elshocht, K. De Meyer, M. Jurczak, P. Absil, S. Biesemans, T. Hoffmann
We discuss several advancements over our previous report [1]: - Introduction of conventional stress boosters resulting in 16% and 11% for nMOS and pMOS respectively. For the first time the compatibility of SMT (Stress memorization technique) with High-κ/Metal Gate is demonstrated. In addition, we developed a blanket SMT process that does not require a photo to protect the pMOS by selecting a hydrogen-rich SiN film. - A comprehensive study of HfSiO and HfO2 as function of La/Al doping and spike/laser annealing. Parameters studied include Vt tuning, reliability and process control. - Demonstration of fast invertor delay of 10ps including high frequency response analysis revealing the negative impact of high metal sheet resistance and parasitic metal-poly interface oxide.
Kubicek, S, Schram, T, Rohr, E, Paraschiv, V, Vos, R, Demand, M, Adelmann, C, Witters, T, Nyns, L, Delabie, A, Ragnarsson, LÃ…, Chiarella, T, Kerner, C, Mercha, A, Parvais, B, Aoulaiche, M, Ortolland, C, Yu, H, Veloso, A, Witters, L, Singanamalla, R, Kauerauf, T, Brus, S, Vrancken, C, Chang, VS, Chang, SZ, Mitsuhashi, R, Okuno, Y, Akheyar, A, Cho, HJ, Hooker, J, O'Sullivan, BJ, Van Elshocht, S, De Meyer, K, Jurczak, M, Absil, P, Biesemans, S & Hoffmann, T 2008, Strain enhanced low-VT CMOS featuring La/Al-doped HfSiO/TaC and 10ps invertor delay. in Proceedings - CIS Workshops 2007, 2007 International Conference on Computational Intelligence and Security Workshops, CISW 2007., 4588590, Digest of Technical Papers - Symposium on VLSI Technology, pp. 130-131, 2008 Symposium on VLSI Technology Digest of Technical Papers, VLSIT, Honolulu, HI, United States, 17/06/08. https://doi.org/10.1109/VLSIT.2008.4588590
Kubicek, S., Schram, T., Rohr, E., Paraschiv, V., Vos, R., Demand, M., Adelmann, C., Witters, T., Nyns, L., Delabie, A., Ragnarsson, L. Ã…., Chiarella, T., Kerner, C., Mercha, A., Parvais, B., Aoulaiche, M., Ortolland, C., Yu, H., Veloso, A., ... Hoffmann, T. (2008). Strain enhanced low-VT CMOS featuring La/Al-doped HfSiO/TaC and 10ps invertor delay. In Proceedings - CIS Workshops 2007, 2007 International Conference on Computational Intelligence and Security Workshops, CISW 2007 (pp. 130-131). Article 4588590 (Digest of Technical Papers - Symposium on VLSI Technology). https://doi.org/10.1109/VLSIT.2008.4588590
@inproceedings{51cf1eaeab8143809bcc4ba3ddc7611b,
title = "Strain enhanced low-VT CMOS featuring La/Al-doped HfSiO/TaC and 10ps invertor delay",
abstract = "We discuss several advancements over our previous report [1]: - Introduction of conventional stress boosters resulting in 16% and 11% for nMOS and pMOS respectively. For the first time the compatibility of SMT (Stress memorization technique) with High-κ/Metal Gate is demonstrated. In addition, we developed a blanket SMT process that does not require a photo to protect the pMOS by selecting a hydrogen-rich SiN film. - A comprehensive study of HfSiO and HfO2 as function of La/Al doping and spike/laser annealing. Parameters studied include Vt tuning, reliability and process control. - Demonstration of fast invertor delay of 10ps including high frequency response analysis revealing the negative impact of high metal sheet resistance and parasitic metal-poly interface oxide.",
author = "S. Kubicek and T. Schram and E. Rohr and V. Paraschiv and R. Vos and M. Demand and C. Adelmann and T. Witters and L. Nyns and A. Delabie and Ragnarsson, {L. {\AA}} and T. Chiarella and C. Kerner and A. Mercha and B. Parvais and M. Aoulaiche and C. Ortolland and H. Yu and A. Veloso and L. Witters and R. Singanamalla and T. Kauerauf and S. Brus and C. Vrancken and Chang, {V. S.} and Chang, {S. Z.} and R. Mitsuhashi and Y. Okuno and A. Akheyar and Cho, {H. J.} and J. Hooker and O'Sullivan, {B. J.} and {Van Elshocht}, S. and {De Meyer}, K. and M. Jurczak and P. Absil and S. Biesemans and T. Hoffmann",
year = "2008",
month = sep,
day = "29",
doi = "10.1109/VLSIT.2008.4588590",
language = "English",
isbn = "9781424418053",
series = "Digest of Technical Papers - Symposium on VLSI Technology",
pages = "130--131",
booktitle = "Proceedings - CIS Workshops 2007, 2007 International Conference on Computational Intelligence and Security Workshops, CISW 2007",
note = "2008 Symposium on VLSI Technology Digest of Technical Papers, VLSIT ; Conference date: 17-06-2008 Through 19-06-2008",
}