A 10GHz FMCW subsampling PLL is presented, that uses a low-power charge-integrating QDAC to tune the VCO for wideband low-noise modulation. Nonlinearities in the QDAC modulation path are corrected within 700µsec cold start-up, followed by a full on-chip background calibration engine to track supply and temperature variations. The PLL consumes 11.7mW (of which <0.5mW in the QDAC) to generate a 23.6MHz/µs chirp slope with 89kHz rms-frequency-error for 1.21GHz chirp-bandwidth.
Renukaswamy, P, Markulic, N, Park, S, Kankuppe Raghavendra Swamy, A, Shi, Q, Wambacq, P & Craninckx, J 2020, A 12mW 10GHz FMCW PLL Based on an Integrating DAC with 90kHz rms Frequency Error for 23MHz/μs Slope and 1.2GHz Chirp Bandwidth. in 2020 International Solid-State Circuits Conference., 17.7, Institute of Electrical and Electronics Engineers ( IEEE ), San Francisco, pp. 278-280, 2020 International Solid-State Circuits Conference, SAN FRANCISCO, Belgium, 16/02/20. https://doi.org/10.1109/ISSCC19947.2020.9063080
Renukaswamy, P., Markulic, N., Park, S., Kankuppe Raghavendra Swamy, A., Shi, Q., Wambacq, P., & Craninckx, J. (2020). A 12mW 10GHz FMCW PLL Based on an Integrating DAC with 90kHz rms Frequency Error for 23MHz/μs Slope and 1.2GHz Chirp Bandwidth. In 2020 International Solid-State Circuits Conference (pp. 278-280). Article 17.7 Institute of Electrical and Electronics Engineers ( IEEE ). https://doi.org/10.1109/ISSCC19947.2020.9063080
@inproceedings{9eda17aff0bc44668e1d24b5ca51e585,
title = "A 12mW 10GHz FMCW PLL Based on an Integrating DAC with 90kHz rms Frequency Error for 23MHz/μs Slope and 1.2GHz Chirp Bandwidth",
abstract = "A 10GHz FMCW subsampling PLL is presented, that uses a low-power charge-integrating QDAC to tune the VCO for wideband low-noise modulation. Nonlinearities in the QDAC modulation path are corrected within 700µsec cold start-up, followed by a full on-chip background calibration engine to track supply and temperature variations. The PLL consumes 11.7mW (of which <0.5mW in the QDAC) to generate a 23.6MHz/µs chirp slope with 89kHz rms-frequency-error for 1.21GHz chirp-bandwidth.",
keywords = "PLL, FMCW radar, Sub-sampling PLL, Integrating DAC, Background calibration",
author = "Pratap Renukaswamy and Nereo Markulic and Sehoon Park and \{Kankuppe Raghavendra Swamy\}, Anirudh and Qixian Shi and Piet Wambacq and Jan Craninckx",
year = "2020",
month = feb,
day = "18",
doi = "10.1109/ISSCC19947.2020.9063080",
language = "English",
pages = "278--280",
booktitle = "2020 International Solid-State Circuits Conference",
publisher = "Institute of Electrical and Electronics Engineers ( IEEE )",
note = "2020 International Solid-State Circuits Conference ; Conference date: 16-02-2020 Through 20-02-2020",
url = "http://submissions2.mirasmart.com/ISSCC2020/PDF/ISSCC2020AdvanceProgram.pdf",
}