We present an analog subsampling PLL based on a digital-to-time converter (DTC), which operates with almost no performance gap (176/198 fs RMS jitter) between the integer and the worst case fractional operation, achieving -246.6 dB FOM in the worst case fractional mode. The PLL is capable of two-point, 10 Mbit/s GMSK modulation with -40.5 dB EVM around a 10.24 GHz fractional carrier. The analog nonidealities-DTC gain, DTC nonlinearity, modulating VCO bank gain, and nonlinearity-are calibrated in the background while the system operates normally. This results in \textasciitilde{}15 dB fractional spur improvement (from -41 dBc to -56.5 dBc) during synthesis and \textasciitilde{}15 dB EVM improvement (from -25 dB to -40.5 dB) during modulation. The paper provides an overview of the mechanisms that contribute to performance degradation in DTC-based PLL/phase modulators and presents ways to mitigate them. We demonstrate state-of-the-art performance in nanoscale CMOS for fractional-N synthesis and phase modulation.
Markulic, N, Raczkowski, K, Martens, E, Paro Filho, PE, Hershberg, B, Wambacq, P & Craninckx, J 2016, 'A DTC-Based Subsampling PLL Capable of Self-Calibrated Fractional Synthesis and Two-Point Modulation', IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. PP, no. 99, DOI: 10.1109/JSSC.2016.2596766, pp. 1-15. https://doi.org/10.1109/JSSC.2016.2596766
Markulic, N., Raczkowski, K., Martens, E., Paro Filho, P. E., Hershberg, B., Wambacq, P., & Craninckx, J. (2016). A DTC-Based Subsampling PLL Capable of Self-Calibrated Fractional Synthesis and Two-Point Modulation. IEEE JOURNAL OF SOLID-STATE CIRCUITS, PP(99), 1-15. Article DOI: 10.1109/JSSC.2016.2596766. https://doi.org/10.1109/JSSC.2016.2596766
@article{89e443025a2d4f7aa7271850b0d6394b,
title = "A DTC-Based Subsampling PLL Capable of Self-Calibrated Fractional Synthesis and Two-Point Modulation",
abstract = "We present an analog subsampling PLL based on a digital-to-time converter (DTC), which operates with almost no performance gap (176/198 fs RMS jitter) between the integer and the worst case fractional operation, achieving -246.6 dB FOM in the worst case fractional mode. The PLL is capable of two-point, 10 Mbit/s GMSK modulation with -40.5 dB EVM around a 10.24 GHz fractional carrier. The analog nonidealities-DTC gain, DTC nonlinearity, modulating VCO bank gain, and nonlinearity-are calibrated in the background while the system operates normally. This results in \textasciitilde{}15 dB fractional spur improvement (from -41 dBc to -56.5 dBc) during synthesis and \textasciitilde{}15 dB EVM improvement (from -25 dB to -40.5 dB) during modulation. The paper provides an overview of the mechanisms that contribute to performance degradation in DTC-based PLL/phase modulators and presents ways to mitigate them. We demonstrate state-of-the-art performance in nanoscale CMOS for fractional-N synthesis and phase modulation.",
keywords = "PLL, bacground calibraiton, digital-to-time converter, divider-less, frequency synthesis, modulation, polar modulation",
author = "Nereo Markulic and Kuba Raczkowski and Ewout Martens and \{Paro Filho\}, \{Pedro Emiliano\} and Benjamin Hershberg and Piet Wambacq and Jan Craninckx",
year = "2016",
month = oct,
day = "5",
doi = "10.1109/JSSC.2016.2596766",
language = "English",
volume = "PP",
pages = "1--15",
journal = "IEEE JOURNAL OF SOLID-STATE CIRCUITS",
issn = "0018-9200",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "99",
}