Huynh, B. T., Sakhare, S., Ryckaert, J., Yakimets, D., Mercha, A., Verkest, D., Thean, A., & Wambacq, P. (2015). Design technology co-optimization for enabling 5nm gate-all-around nanowire 6T SRAM. In IC Design & Technology (ICICDT), 2015 International Conference on (pp. 1-4). IEEE. https://doi.org/10.1109/ICICDT.2015.7165874

@inproceedings{676b2112271842daa8d0f83f576195df,
title = "Design technology co-optimization for enabling 5nm gate-all-around nanowire 6T SRAM",
abstract = "This paper presents a comprehensive benchmarking and co-optimization of 6T SRAM bitcells designed with 5nm vertical and lateral gate-all-around nanowire FET technology for the first time. A variety of 6T SRAM bitcells configurations combined with different device integration scenarios will be discussed. Our results show that an ultra-dense SRAM bitcell (0.01 um2) can be achieved with vertical FET architecture. The bitcell designed with vertical FET are preferably targeted for low power applications while the lateral FET-based SRAM bitcells could provide 4.5x higher in performance, but resulting in a penalty of 17x increasing in the leakage current compared to the vertical designs. A Vmin of 0.45 V could be obtained for 122 SRAM bitcells implemented with vertical devices.",
keywords = "5nm, 6T SRAM, CMOS scaling, DTCO, Vmin, Embedded memory, gate-all-around FETs, nonowire, on-chip variation, parametric yield, vertical FET",
author = "Huynh, {Bao Trong} and Sushil Sakhare and Julien Ryckaert and Dmitry Yakimets and Abdelkarim Mercha and Diederik Verkest and Aaron Thean and Piet Wambacq",
year = "2015",
month = jun,
day = "1",
doi = "10.1109/ICICDT.2015.7165874",
language = "English",
pages = "1--4",
booktitle = "IC Design & Technology (ICICDT), 2015 International Conference on",
publisher = "IEEE",
note = "2015 International Conference on IC Design & Technology (ICICDT) ; Conference date: 01-06-2015 Through 03-06-2015",
}