Johan Stiens participated as Belgian representative of BSMBEC-NCBME this morning to the “European Parliament Interest Group on Biomedical Engineering”

The fourth meeting with European Parliament Members took place in hybrid mode on March 21, 2023, on the premises of the European Parliament hosted by MEP Stelios Kympouropoulos with the support of the European Alliance of Medical and Biological Engineering and Science (EAMBES) as part of a week dedicated to the role of technology in health. The event was entitled: “Pandemic Management and Preparedness – Telemedicine and the Role of Innovative Technologies in Securing a Safer Future”.  Please find here the final Agenda of the meeting.

Fawaz Sammani obtained the Honourable Mention award at the ICCVW on Vision and Language Algorithmic Reasoning (VLAR 2023) for the paper:  F. Sammani, N. Deligiannis, “Unifying Textual Explanations for Vision and Vision-Language Tasks”, ICCV Workshop and Challenge on Vision and Language Algorithmic Reasoning (VLAR 2023

After two years of dedicated research and development under the leadership of ETRO-VUB, a breakthrough has been achieved within the INTOWALL project: a revolutionary radar technology for building inspection was developed, called the transient radar method (TRM). The initiative aimed to reduce the CO2 emissions of buildings and increase their energy efficiency.

The new technology enables the measurement of the density of glass wool in cavity walls with unprecedented precision, without the need for invasive methods. “This advancement not only promises to improve the accuracy of insulation assessments but also contributes to the ambition to achieve a CO2-neutral status by 2050,” says Professor Johan Stiens of ETRO.

Looking towards the future, the project team is focused on further refining the technology to map a wide range of insulation materials and building elements. This prospect of expansion and application on a larger scale highlights the endless possibilities. As part of the FTI Brussels Festival, the milestone of the INTOWALL project will be celebrated. A unique demonstration was held on March 18, 2024.

Additionally, the project team invites potential partners to contribute to and participate in this groundbreaking endeavour. Through collaboration, we can transform the construction sector into a more sustainable and efficient future.

For more information on InToWall press articles: https://press.vub.ac.be/wereldprimeur-in-radartechnologie and https://trends.knack.be/kanaal-z/z-nieuws/bekijk-radar-van-vub-ziet-isolatie-dwars-door-muren-heen/

Knowledge Engineering in Diagnostic Imaging – a huge project on AI in medical image analysis, the foundation of the internal ETRO ICT computer network.

On February 8 2023 at 16.00, Pratap Renukaswamy will defend his PhD entitled “PLL MODULATION AND MIXED-SIGNAL CALIBRATION TECHNIQUES FOR FMCW CHIRP SYNTHESIS”.

Everybody is invited to attend the presentation in room D.2.01, or though this link.

Radar sensors have moved in the past decade from bulky systems to integrated solutions, driven by many applications in varying domains. Radar sensors are key components in self-driving cars to provide robust sensing capabilities in every weather condition. They allow contactless monitoring of vital signs such as breathing and heart rate. One of the latest applications is gesture recognition in recent smartphones.

The signals used in radar sensors are modulated signals: Frequency- Modulated Continuous-Wave (FMCW) is today the most widely used modulation. Here a carrier frequency is linearly modulated to reach a maximum over a specified period. This waveform is called a chirp.

The key component to realize this is a frequency-chirping Phase-Locked Loop (PLL), that generates an clean sinewave of a linearly increasing frequency. Many of the key performance criteria of the radar system are determined by the quality of the generated FMCW source. Any nonlinearity in the frequency versus time curve causes errors in the detected distance and speed. Any noise in the system will prevent the detection of small targets, hidden in the noise floor. The total available bandwidth (difference between maximum and minimum frequency) that can be generated determines the range resolution of the radar, where several GHz of bandwidth are required to detect targets with cm accuracy.

To address these challenges, this thesis presents a PLL modulation architecture and circuit blocks for low-power and high-performance chirp synthesis and verified using two 28 nm CMOS prototype chips. The designs will further push the performance of the FMCW PLLs, by combining innovative mixed-signal processing and calibration techniques with Charge-Integrating Digital-to-Analog Converter (QDAC) as a key building block. The 10 GHz sub-sampling PLL prototype achieves 23 MHz/μs chirp slope with 28 kHz rms-FM-error, while consuming less than 12 mW power. The 16 GHz duty-cycled charge-pump PLL design achieves a 29 MHz/μs slope with an rms-FM-error below 41 kHz while consuming less than 16.5 mW.

On October 13th 2023 at 15.30, Johan Hoang-Dung Nguyen will defend his PhD entitled “HIGH-EFFICIENCY TRANSMITTERS FOR 5G COMMUNICATION AT MMWAVE FREQUENCIES”.

Everybody is invited to attend the presentation at the Room D.2.01, or digitally via this link.

The fifth generation (5G) wireless communication technology started its deployment in 2019 to meet the increasing global demands for highspeed connectivity. The radio frequency spectrum will be progressively expanded to millimeter-wave ranges to meet the growing demand for mobile broadband applications. 5G targets wireless data rates of up to 10 Gbit/s. A broad deployment of applications that are based on these high data rates is only possible if the power consumption of the transmit and receive part does not grow out of hand. In a mm-wave transceiver, the transmit part often consumes most of the energy. This doctoral work focuses on the design and calibration of digital polar transmit architectures operating at mm-wave frequencies, which could bring a high data rate for less power consumption. In a polar transmitter, the signal is split in amplitude path and a phase path. The amplitude is modulated using a so-called RF-DAC, while the phase is modulated via phase modulators.

One big design achievement of this Ph.D. work is the 60-GHz digital polar chip in 28-nm Bulk CMOS. Compared to earlier digital polar transmitters operating around 60GHz, the RF-DAC used here does not suffer from leakage from disabled cells. In this way, it is possible to modulate with a higher modulation depth. Two leakage reduction techniques have been suggested from which a patent is issued: the dynamic driver and the inverter switch. The phase modulator is a Cartesian one, using a 90 degrees hybrid, that splits the input signal into an in-phase (I) and a quadrature (Q) component, which are weighted with a very linear variable gain, made with variable-gain amplifiers (VGAs). Thanks to this phase modulator and to the leakage-mitigation improvements, this chipachieves a raw data rate of 10.52 Gb/s using a 64-QAM modulation. The on-chip impedance matching is accomplished with transformers. In this work, a design flow based on ABCD matrices has been developed to speed up the design of these transformers. The same framework is later used to design a 140-GHz transceiver front-end with a transmit/receive switch.

Synchronization between the amplitude path and the phase path is vital in digital polar architectures. To facilitate and speed up this synchronization, a non-iterative method is proposed here. This strategy is then extended to retrieve and compensate AM-AM and AM-PM distortion from the VGAs. It is also possible to estimate the IQ imbalance of the hybrid. Higher bandwidths can be achieved by using the method to calculate an equalization filter for the phase samples.