ETRO-VUB was represented at imec’s ITF World 2026, participating in the “The Future of Media and Entertainment” event.

Rodolphe Valicon De Soete, Colas Schretter, and David Blinder contributed to the sessions on the StageTech Flanders volumetric capturing roadmap and holographic display technology.

They presented a demo showcasing interactive rendering using Gaussian mixture models and holography on a light-field display. Many thanks to Rodolphe and Colas for preparing and presenting the demo at ITF World!

On May 9 2022 at 14.00 Zhiwei Zong will defend his PhD entitled “DESIGN OF VCOs AND PAs IN 22 NM FD-SOI FOR 5G MM-WAVE COMMUNICATIONS”.

Everybody is invited to attend the presentation online via this TEAMS link.

The use of spectrum in the millimeter-wave (mm-Wave) frequency range is considered as a key enabler to continue the insatiable demand for increased wireless data capacity. This spectrum will be adopted in the 5G wireless communication standard. To obtain a high integration degree for the implementation of 5G mm-Wave transceivers, advanced CMOS is the preferred technology. The higher operating frequency, compared to 4G, poses more design challenges on the key building blocks of a transceiver. This PhD thesis focuses on the design of the two key building blocks in a 5G mm-Wave transceiver, namely a voltage-controlled oscillator (VCO) and a power amplifier (PA). All building blocks designed in this PhD work are operating in the 20-30 GHz frequency region. All building blocks have been designed in a 22nm fully-depleted silicon-on-insulator (FD-SOI) CMOS technology.

First, a modified transformer-feedback VCO (TF-VCO) with a sourcebridging capacitor (Cs) is introduced. Thanks to the use of Cs, the phase noise (PN) in the 1/f2 and 1/f3 regions are both improved compared to earlier published TF-VCOs. The origin of the PN improvement by the use Cs is explained in this thesis. It is seen that with Cs we can improve the symmetry of the waveform of the voltage over the tank of the VCO. Also, with Cs the effective quality factor of the transformer can be increased, which also reduces phase noise. These theoretical investigations are proven with measurement results. With a second design, an LC-VCO design, another key design challenge is tackled, namely the suppression of flicker noise upconversion. A 22-29GHz voltage-biased LC-VCO is designed and implemented to suppress this flicker noise upconversion by using a flicker noise filtering technique. A self-coupled inductor and a common-centroid capacitor bank layout are proposed in this design to guarantee a good flicker noise suppression over the frequency tuning range.

Next, two 28GHz PAs are designed and implemented for 5G mm-Wave communications. The first PA focuses on generation of a high output power (Pout) with a high linearity. This is achieved in a first design that uses a two-way current combiner and an output stage that uses stacking of transistors. The stack of three transistors used in this design enables the generation of a high output power without overstressing the core devices. The second PA focuses on the power back-off (PBO) efficiency enhancement. This is important for communication with a high spectral efficiency: high-order modulation requires to operate at a relatively large back-off from the saturation level. The design is based on the Doherty architecture. By merging lumped passive components into a transformer, a transformer-based Doherty PA with a compact power combiner is obtained, achieving Doherty load modulation with a compact footprint. This design has the highest power density and ITRS PA figure-of-merit (FOM) among the published mm-wave Doherty PAs.

On March 29th 2024 at 16::00, Lucas Santana will defend their PhD entitled “TOWARDS UNCHARTED TERRITORIES: HIGH-PERFORMANCE AND HIGH-BANDWIDTH RINGAMP-BASED DELTA-SIGMA ADCs”.

Everybody is invited to attend the presentation in room D.2.01, or digitally via this link.

Analog-to-digital (ADC) research often happens in an agnostic detachment from the intended application; although motivation is sometimes presented, it is not always implemented with the proposed prototype. Advancements in ADC linearity and speed enable applications that were nonexistent before to emerge, such as direct RF conversion and 8k camera recording. Most ADC architectures cover all regions of the performance space, being at the forefront of the state-of-the-art for some areas and not so much for others. This high coverage enables the use of the advantages and peculiarities of different architectures across different applications. One notable architecture that does not perform this is the Discrete Time (DT) Delta-Sigma Modulator (DSM) ADC, in which the published state-of-the-art bandwidth front is limited to 20 MHz. This work investigates this limitation, showing that it can be overcome with high-efficiency ring amplifiers (ringamps) and the correct design process. This work presents a prototype for a single loop 3rd-order DT DSM ADC based on ringamps for the loop filter that could double the bandwidth reached by DT DSM ADC at 47.5 MHz and achieve 67 dB of signal-tonoise and distortion ratio (SNDR) when clocked at 950 MHz. It also shows outstanding figures of merit (FoM): the Schreier FoM, FoMs is 167 dB and the Walden FoM, FoMw is 27 fJ per conversion step. The second prototype used time interleaving to improve the sampling rate and bandwidth further and used a noise-coupled (NC) noiseshaping (NS) SAR quantizer to enable aliased noise suppression. It achieved 1.4 GS/s of sampling rate, a decimated bandwidth of 70 MHz at a peak SNDR of 67 dB, with a power consumption of 32 mW; this translated to a FoMs of 160 dB and a FoMw of 143 fJ/c.s. Both prototypes were the first to pave the way to increase the bandwidth in DT DSM ADC efficiently and can still benefit from recent developments in ringamps and noise-shaping SAR ADCs, leading the architecture to conquer even more space in this uncharted territory.

ETRO contributes via Johan Stiens, as member of the  AIOTI Digital for Climate Task Force, to the second release of the carbon footprint measurement methodology for users of IoT and Edge Computing technologies and services

The Report is structured to present rules and regulations of the European Green Deal, the initiatives and standards, and existing methodologies of measuring ICT carbon footprint. The report also includes how those methodologies can be applied to IoT and Edge Computing, the description of the methodologies, selection criteria and how to measure benefits of using them in reducing carbon footprint by using IoT and Edge Computing technologies and services for several industrial domains.

This second version of the report updates the equations that were introduced in version (Release 1.1) of the Report, which address the calculation of avoided carbon emissions in industrial sectors when ICT is applied by focusing on:

• a baseline (industrial) scenario that is supported by an ICT solution and a green enabled (industrial) scenario that apply an advanced ICT solution to reduce carbon emissions in the same industrial scenario,
• the impact that a closed loop recycling/allocation process has on these equations.

Weblink to the full report: https://aioti.eu/iot-and-edge-computing-carbon-footprint-measurement-methodology-report-release-2/

ETRO-VUB was pleased to participate in the first Climate Technology Day at Green Energy Park vzw, organised by FACT-VUB and Vrije Universiteit Brussel.

ETRO-VUB was represented by Prof. Johan Stiens, who joined VUB colleagues in welcoming students from different secondary schools for interactive sessions on engineering and climate technology.

The event offered students the opportunity to discover how research and innovation in areas such as electric mobility, sustainable energy systems, and climate technology can help shape a more sustainable future.

We are proud to have contributed to an inspiring day that encouraged the next generation of engineers to engage with one of the most important challenges of our time: tackling climate change.

The world needs climate engineers.

Many thanks to FACT-VUB, Green Energy Park vzw, Vrije Universiteit Brussel, VUB Faculty of Engineering, and all colleagues and partners involved for making this event possible.

On June 14 2023 at 11.00, Priscilla Benedetti will defend her PhD entitled “SERVERLESS TECHNOLOGIES AND ARTIFICIAL INTELLIGENCE FOR EDGE SERVICE MANAGEMENT”.

Everybody is invited to attend the presentation at the Aula Magna (Great Hall) of the Department of Engineering, University of Perugia (Address: via Goffredo Duranti 93, Perugia) or online via this link.

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The emergence of the Internet of Things (IoT) ecosystem has exponentially increased the need for real-time and data-intensive applications. It has shifted the computing load from the centralized cloud to peripheral nodes, hence introducing the adoption of edge computing. In edge computing, services are deployed closer to the users and IoT devices. Edge computing provides computation and storage on geographically distributed nodes, some with limited resources. For this reason, resource efficiency and flexibility is fundamental in edge services: To tackle this challenge, serverless computing can be leveraged. It allows to efficiently deploy containerized applications on resource constrained nodes. It aims at providing the required Quality Of Service (QoS) while limiting resource consumption and allows scaling with traffic volume.
In this context, our work aims at analyzing and developing serverlessbased technologies for edge computing applications. It evaluates the use of Artificial Intelligence, namely Reinforcement Learning (RL) techniques, to optimize the scalability and resource efficiency of serverless frameworks on edge computing clusters. The study will be divided into two main focus areas: Firstly, an experimental analysis of serverless computing for IoT and 5G services is done, considering infrastructures with various features and various open-source software. Secondly, the development and analysis of reinforcement-learning tools to enhance the performance of serverless computing on edge clusters is presented. These tools are evaluated on various IoT-based applications, from simple lightweight webservers to complex stream processing pipelines.
Given the growing traction of serverless computing in both academia and industry, the analysis and tools included in this study will provide important insights on its benefits and drawbacks, while enhancing serverless computing performance for edge services deployment and management.